1. Field
Integrated circuit processing.
2. Background
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send or receive signals external to the chip. Popular types of interconnections include aluminum alloy interconnections and copper or copper alloy interconnections.
One process used to form interconnections, particularly copper or copper alloy interconnections, is a damascene process. In a damascene process, a trench is cut in a dielectric and filled with copper to form the interconnection. A via may be in the dielectric beneath the trench with a conductive material in the via to couple the interconnection to underlying integrated circuit devices or underlying interconnections. In one damascene process (a “dual damascene process”), the trench and via are each filled with copper material by, for example, a single deposition.
A photoresist is typically used over the dielectric to pattern a via or a trench or both in the dielectric for the interconnection. After patterning, the photoresist is removed. The photoresist is typically removed by an oxygen plasma (oxygen ashing). The oxygen used in the oxygen ashing can react with an underlying copper interconnection and oxidize the interconnection. Accordingly, damascene processes typically employ an etch stop layer of silicon nitride (Si3N4) directly over the copper interconnection to protect the copper from oxidation during oxygen ashing in the formation of a subsequent level interconnection. In intelayer interconnection levels (e.g., beyond a first level over a device substrate), the etch stop layer also protects against misguided or unlanded vias extending to an underlying layer or level.
In general, the Si3N4 etch stop layer is very thin, for example, roughly 10 percent of the thickness of the pre-metal dielectric (PMD) layer or interlayer dielectric (ILD) layer. A thin etch stop layer is preferred primarily because Si3N4 has a relatively high dielectric constant (k) on the order of 6 to 7. The dielectric constant of a dielectric material, such as an interlayer dielectric, generally describes the parasitic capacitance of the material. As the parasitic capacitance is reduced, the cross-talk (e.g., a characterization of the electric field between adjacent interconnections) is reduced, as is the resistance-capacitance (RC) time delay and power consumption. Thus, the effective dielectric constant (keff) of a PMD layer or ILD layer is defined by the thin etch stop layer and another dielectric material having a lower dielectric constant so that the effect of the high dielectric material typically used for the etch stop layer (e.g., Si3N4) is minimized.